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M95256
256Kbit Serial SPI Bus EEPROM With High Speed Clock
FEATURES SUMMARY s Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes)
s
Figure 1. Packages
Single Supply Voltage: - 4.5 to 5.5V for M95256 - 2.5 to 5.5V for M95256-W - 1.8 to 3.6V for M95256-S
s
High speed - 5MHz Clock Rate, 10ms Write Time (current product: identified by process identification letter S) - 10MHz Clock Rate, 5ms Write Time (new product: identified by process identification letter V) Details of how to find the process identification letter are given on page 33).
8 1
PDIP8 (BN)
s s s s s s s s
Status Register Hardware Protection of the Status Register BYTE and PAGE WRITE (up to 64 Bytes) Self-Timed Programming Cycle Adjustable Size Read-Only EEPROM Area Enhanced ESD Protection More than 100,000 Erase/Write Cycles More than 40 Year Data Retention
8 1
SO8 (MN) 150 mil width
8 1
SO8 (MW) 200 mil width
June 2003
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M95256
SUMMARY DESCRIPTION These electrically erasable programmable memory (EEPROM) devices are accessed by a high speed SPI-compatible bus. The memory array is organized as 32768 x 8 bit. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 2. The device is selected when Chip Select (S) is taken Low. Communications with the device can be interrupted using Hold (HOLD). Figure 2. Logic Diagram
VCC
Note: 1. See page 30 (onwards) for package dimensions, and how to identify pin-1.
Figure 3. DIP and SO Connections
M95xxx S Q W VSS 1 2 3 4 8 7 6 5
AI01790D
VCC HOLD C D
D C S W HOLD M95xxx
Q
Table 1. Signal Names
C D Q Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground
S
W HOLD
VSS
AI01789C
VCC VSS
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M95256
SIGNAL DESCRIPTION During all operations, V CC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held High or Low (according to voltages of VIH, VOH, VIL or VOL, as specified in Tables 13 to 18). These signals are described next. Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select (S). When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby mode. Driving Chip Select (S) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. Hold (HOLD). The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. Write Protect (W). The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either High or Low, and must be stable during all write operations.
CONNECTING TO THE SPI BUS These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes Low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. Figure 4 shows three devices, connected to an MCU, on a SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the others being high impedance.
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M95256
Figure 4. Bus Master and Memory Devices on the SPI Bus
SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK CQD Bus Master (ST6, ST7, ST9, ST10, Others) SPI Memory Device CS3 CS2 CS1 S W HOLD S W HOLD S W HOLD SPI Memory Device SPI Memory Device CQD CQD
AI03746D
Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
SPI Modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: - CPOL=0, CPHA=0 - CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data Figure 5. SPI Modes Supported
CPOL CPHA C
is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in Stand-by mode and not transferring data: - C remains at 0 for (CPOL=0, CPHA=0) - C remains at 1 for (CPOL=1, CPHA=1)
0
0
1
1
C
D
MSB
Q
MSB
AI01438B
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M95256
OPERATING FEATURES Power-up When the power supply is turned on, V CC rises from VSS to VCC. During this time, the Chip Select (S) must be allowed to follow the V CC voltage. It must not be allowed to float, but should be connected to VCC via a suitable pull-up resistor. As a built in safety feature, Chip Select (S) is edge sensitive as well as level sensitive. After Powerup, the device does not become selected until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select (S) must have been High, prior to going Low to start the first operation. Power On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. The internal reset is held active until VCC has reached the POR threshold value, and all operations are disabled - the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid VCC must be applied before applying any logic signal. Active Power and Stand-by Power Modes When Chip Select (S) is Low, the device is enabled, and in the Active Power mode. The device consumes ICC, as specified in Tables 13 to 18. When Chip Select (S) is High, the device is disabled. If an Erase/Write cycle is not currently in progress, the device then goes in to the Stand-by Power mode, and the device consumption drops to ICC1. Hold Condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To enter the Hold condition, the device must be selected, with Chip Select (S) Low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as Serial Clock (C) already being Low (as shown in Figure 6). The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C) already being Low. Figure 6 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being Low.
Power-down At Power-down, the device must be deselected. Chip Select (S) should be allowed to follow the voltage applied on V CC.
Figure 6. Hold Condition Activation
C
HOLD
Hold Condition
Hold Condition
AI02029D
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Status Register Figure 7 shows the position of the Status Register in the control logic of the device. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. BP1, BP0 bits. The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. SRWD bit. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits. device features the following data protection mechanisms: s Write and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.
s
All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Write (WRITE) instruction completion
s
The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits to be protected. This is the Hardware Protected Mode (HPM).
s
Table 2. Status Register Format
b7 SRWD 0 0 0 BP1 BP0 WEL b0 WIP
Status Register Write Protect Block Protect Bits Write Enable Latch Bit Write In Progress Bit
Data Protection and Protocol Control Non-volatile memory devices can be used in environments that are particularly noisy, and within applications that could experience problems if memory bytes are corrupted. Consequently, the
For any instruction to be accepted, and executed, Chip Select (S) must be driven High after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). Two points need to be noted in the previous sentence: - The `last bit of the instruction' can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions). - The `next rising edge of Serial Clock (C)' might (or might not) be the next bus transaction for some other device on the SPI bus.
Table 3. Write-Protected Block Size
Status Register Bits Protected Block BP1 0 0 1 1 BP0 0 1 0 1 none Upper quarter Upper half Whole memory none 6000h - 7FFFh 4000h - 7FFFh 0000h - 7FFFh Array Addresses Protected
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MEMORY ORGANIZATION The memory is organized as shown in Figure 7. Figure 7. Block Diagram
HOLD W S C D Q Control Logic
High Voltage Generator
I/O Shift Register
Address Register and Counter
Data Register Status Register
Size of the Read only EEPROM area
Y Decoder
1 Page
X Decoder
AI01272C
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M95256
INSTRUCTIONS Each instruction starts with a single-byte code, as summarized in Table 4. If an invalid instruction is sent (one not contained in Table 4), the device automatically deselects itself.
Table 4. Instruction Set
Instruc tion WREN WRDI RDSR WRSR READ WRITE Description Write Enable Write Disable Read Status Register Write Status Register Read from Memory Array Write to Memory Array Instruction Format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010
Figure 8. Write Enable (WREN) Sequence
S 0 C Instruction D High Impedance Q
AI02281E
1
2
3
4
5
6
7
Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven Low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High.
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M95256
Figure 9. Write Disable (WRDI) Sequence
S 0 C Instruction D High Impedance Q
AI03750D
1
2
3
4
5
6
7
Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven Low, and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: - Power-up - WRDI instruction execution - WRSR instruction completion - WRITE instruction completion.
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M95256
Figure 10. Read Status Register (RDSR) Sequence
S 0 C Instruction D Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB
AI02031E
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Status Register Out 6 5 4 3 2 1 0 7
Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 10. The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch
is reset and no Write or Write Status Register instruction is accepted. BP1, BP0 bits. The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. SRWD bit. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution.
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Figure 11. Write Status Register (WRSR) Sequence
S 0 C Instruction Status Register In 7 High Impedance Q
AI02282D
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
D
6
5
4
3
2
1
0
MSB
Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on Serial Data Input (D). The instruction sequence is shown in Figure 11. The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the Status Register. b6, b5 and b4 are always read as 0. Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the selftimed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0) bits are frozen at their current values from just before the start of the execution of Write Status Register (WRSR) instruction. The new, updated, values take effect at the moment of completion of the execution of Write Status Register (WRSR) instruction.
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Table 5. Protection Modes
W Signal 1 0 SRWD Bit 0 0 Software Protected (SPM) Mode Write Protection of the Status Register Status Register is Writable (if the WREN instruction has set the WEL bit) The values in the BP1 and BP0 bits can be changed Status Register is Hardware write protected The values in the BP1 and BP0 bits cannot be changed Memory Content Protected Area1 Unprotected Area1
Write Protected
Ready to accept Write instructions
1
1
0
1
Hardware Protected (HPM)
Write Protected
Ready to accept Write instructions
Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 5.
The protection features of the device are summarized in Table 3. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W): - If Write Protect (W) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. - If Write Protect (W) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction.
(Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: - by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) Low - or by driving Write Protect (W) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W) High. If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.
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Figure 12. Read from Memory Array (READ) Sequence
S 0 C Instruction 16-Bit Address 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D High Impedance Q
15 14 13 MSB
3
2
1
0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7
MSB
AI01793D
Note: The most significant address bits, b15 and b15, are Don't Care.
Read from Memory Array (READ) As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). If Chip Select (S) continues to be driven Low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) High. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
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Figure 13. Byte Write (WRITE) Sequence
S 0 C Instruction 16-Bit Address Data Byte 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D High Impedance Q
15 14 13
3
2
1
0
7
6
5
4
3
2
1
0
AI01795D
Note: The most significant address bits, b15 and b15, are Don't Care.
Write to Memory Array (WRITE) As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) High at a byte boundary of the input data. In the case of Figure 13, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. The self-timed Write cycle starts, and continues for a period tWC (as specified in Tables 19 to 24), at the end of which the Write in Progress (WIP) bit is reset to 0. If, though, Chip Select (S) continues to be driven Low, as shown in Figure 14, the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these devices is 64 bytes). The instruction is not accepted, and is not executed, under the following conditions: - if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) - if a Write cycle is already in progress - if the device has not been deselected, by Chip Select (S) being driven High, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in) - if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
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Figure 14. Page Write (WRITE) Sequence
S 0 C Instruction 16-Bit Address Data Byte 1 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D
15 14 13
3
2
1
0
7
6
5
4
3
2
1
0
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Data Byte 2 Data Byte 3 Data Byte N
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
AI01796D
Note: The most significant address bits, b15 and b15, are Don't Care.
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POWER-UP AND DELIVERY STATE Power-up State After Power-up, the device is in the following state: - Stand-by mode - deselected (after Power-up, a falling edge is required on Chip Select (S) before any instructions can be started). - not in the Hold Condition - the Write Enable Latch (WEL) is reset to 0 - Write In Progress (WIP) is reset to 0 the SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits). Initial Delivery State The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
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M95256
MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 6. Absolute Maximum Ratings
Symbol TSTG TLEAD VO VI VCC VESD Storage Temperature Lead Temperature during Soldering Output Voltage Input Voltage Supply Voltage Electrostatic Discharge Voltage (Human Body model) 2 PDIP: 10 seconds SO: 20 seconds (max) 1 -0.3 -0.3 -0.3 -4000 Parameter Min. -65 Max. 150 260 235 VCC+0.6 6.5 6.5 4000 Unit C C V V V V
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
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M95256
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the MeasureTable 7. Operating Conditions (M95256)
Symbol VCC TA Ambient Operating Temperature (range 3) -40 125 C Supply Voltage Ambient Operating Temperature (range 6) Parameter Min. 4.5 -40 Max. 5.5 85 Unit V C
ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 8. Operating Conditions (M95256-W)
Symbol VCC TA Supply Voltage Ambient Operating Temperature (range 6) Ambient Operating Temperature (range 3)1 Parameter Min. 2.5 -40 -40 Max. 5.5 85 125 Unit V C C
Table 9. Operating Conditions (M95256-S)
Symbol VCC TA Supply Voltage Ambient Operating Temperature Parameter1 Min. 1.8 -40 Max. 3.6 85 Unit V C
Note: 1. This product is under development. For more information, please contact your nearest ST sales office.
Table 10. AC Measurement Conditions
Symbol CL Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Parameter
Min. 100
Max.
Unit pF
50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC
ns V V
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M95256
Figure 15. AC Measurement I/O Waveform
Input Levels 0.8VCC
Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
Table 11. Capacitance
Symbol COUT CIN Parameter Output Capacitance (Q) Input Capacitance (D) Input Capacitance (other pins) Test Condition VOUT = 0V VIN = 0V VIN = 0V Min. Max. 8 8 6 Unit pF pF pF
Note: Sampled only, not 100% tested, at TA=25C and a frequency of 5 MHz.
Table 12. DC Characteristics (M95256, temperature range 6)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 5MHz, VCC = 5 V, Q = open, Current Product 2 C = 0.1VCC/0.9VCC at 10MHz, VCC = 5 V, Q = open, New Product 3 S = VCC , VCC = 5 V, VIN = VSS or VCC, Current Product 2 S = VCC , VCC = 5 V, VIN = VSS or VCC, New Product 3 -0.3 0.7 VCC IOL = 2 mA, VCC = 5 V IOH = -2 mA, VCC = 5 V 0.8 VCC Min. Max. 2 2 4 Unit A A mA mA
ICC
Supply Current
5 10
A A V V V V
ICC1
Supply Current (Stand-by)
2 0.3 VCC VCC+1 0.4
VIL VIH VOL
1
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
VOH1
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards. 2. Current product: identified by Process Identification letter S. 3. New product: identified by Process Identification letter V.
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Table 13. DC Characteristics (M95256, temperature range 3)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 2 MHz, VCC = 5 V, Q = open, Current Product 2 C = 0.1VCC/0.9VCC at 5 MHz, VCC = 5 V, Q = open, New Product 3 S = VCC , VCC = 5 V, VIN = VSS or VCC, Current Product 2 S = VCC , VCC = 5 V, VIN = VSS or VCC, New Product 3 -0.3 0.7 VCC IOL = 2 mA, VCC = 5 V IOH = -2 mA, VCC = 5 V 0.8 VCC Min. Max. 2 2 4 Unit A A mA
ICC
Supply Current
4 20
mA A
ICC1
Supply Current (Stand-by)
5 0.3 VCC VCC+1 0.4
A V V V V
VIL VIH VOL1 VOH1
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards. 2. Current product: identified by Process Identification letter S. 3. New product: identified by Process Identification letter V.
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Table 14. DC Characteristics (M95256-W, temperature range 6)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 2 MHz, VCC = 2.5 V, Q = open, Current Product 1 C = 0.1VCC/0.9VCC at 5 MHz, VCC = 2.5 V, Q = open, New Product 2 S = VCC , VCC = 2.5 V, VIN = VSS or VCC, Current Product1 S = VCC , VCC = 2.5 V VIN = VSS or VCC, New Product2 -0.3 0.7 VCC IOL = 1.5 mA, VCC = 2.5 V IOH = -0.4 mA, VCC = 2.5 V 0.8 VCC Min. Max. 2 2 2 Unit A A mA
ICC
Supply Current
3 2
mA A
ICC1
Supply Current (Stand-by)
1 0.3 VCC VCC+1 0.4
A V V V V
VIL VIH VOL VOH
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Note: 1. Current product: identified by Process Identification letter S. 2. New product: identified by Process Identification letter V.
Table 15. DC Characteristics (M95256-W, temperature range 3)
Symbol ILI ILO ICC ICC1 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Stand-by) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.5 mA, VCC = 2.5 V IOH = -0.4 mA, VCC = 2.5 V 0.8 VCC Test Condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 5 MHz, VCC = 2.5 V, Q = open S = VCC , VCC = 2.5 V, VIN = VSS or VCC -0.3 0.7 VCC Min. Max. 2 2 3 2 0.3 VCC VCC+1 0.4 Unit A A mA A V V V V
Note: 1. New product: identified by Process Identification letter V.
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Table 16. DC Characteristics (M95256-S)
Symbol ILI ILO ICC ICC1 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Stand-by) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 0.15 mA, VCC = 1.8 V IOH = -0.1 mA, VCC = 1.8 V 0.8 VCC Test Condition1 VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 2 MHz, VCC = 1.8 V, Q = open S = VCC, VIN = VSS or VCC , VCC = 1.8 V -0.3 0.7 VCC Min. Max. 2 2 12 0.3 2 0.3 VCC VCC+1 0.3 Unit A A mA A V V V V
Note: 1. This product is under development. For more infomation, please contact your nearest ST sales office. 2. Preliminary data.
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M95256
Table 17. AC Characteristics (M95256, temperature range 6)
Test conditions specified in Table 10 and Table 7 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH 1 tCL 1 tCLCH 2 tCHCL 2 tDVCH tCHDX tHHCH tHLCH tCHHL tCHHH tSHQZ 2 tCLQV tCLQX tQLQH 2 tQHQL 2 tHHQX 2 tHLQZ 2 tW tDIS tV tHO tRO tFO tLZ tHZ tWC tCLH tCLL tRC tFC tDSU tDH Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock High Set-up Time before HOLD Active Clock High Set-up Time before HOLD not Active Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Low-Z HOLD Low to Output High-Z Write Time 0 50 50 50 100 10 20 30 70 40 60 60 100 60 0 20 20 25 25 5 Parameter Min.4 D.C. 90 90 100 90 90 90 90 1 1 15 15 15 20 30 30 25 25 Max.4 5 Min.5 D.C. 15 15 40 25 15 40 40 1 1 Max.5 10 Unit MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. tCH + tCL 1 / fC. 2. Value guaranteed by characterization, not 100% tested in production. 3. To be characterized. 4. Current product: identified by Process Identification letter S. 5. New product: identified by Process Identification letter V.
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M95256
Table 18. AC Characteristics (M95256, temperature range 3)
Test conditions specified in Table 10 and Table 7 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH 1 tCL 1 tCLCH 2 tCHCL 2 tDVCH tCHDX tHHCH tHLCH tCHHL tCHHH tSHQZ 2 tCLQV tCLQX tQLQH 2 tQHQL 2 tHHQX 2 tHLQZ 2 tW tDIS tV tHO tRO tFO tLZ tHZ tWC tCLH tCLL tRC tFC tDSU tDH Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock High Set-up Time before HOLD Active Clock High Set-up Time before HOLD not Active Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Low-Z HOLD Low to Output High-Z Write Time 0 100 100 100 250 10 40 50 140 90 120 120 250 150 0 50 50 50 100 5 Parameter Min.4 D.C. 200 200 200 200 200 200 200 1 1 20 30 70 40 60 60 100 60 Max.4 2 Min.5 D.C. 90 90 100 90 90 90 90 1 1 Max.5 5 Unit MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. tCH + tCL 1 / fC. 2. Value guaranteed by characterization, not 100% tested in production. 3. To be characterized. 4. Current product: identified by Process Identification letter S. 5. New product: identified by Process Identification letter V.
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M95256
Table 19. AC Characteristics (M95256-W, temperature range 6)
Test conditions specified in Table 10 and Table 8 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH 1 tCL 1 tCLCH 2 tCHCL 2 tDVCH tCHDX tHHCH tHLCH tCHHL tCHHH tSHQZ 2 tCLQV tCLQX tQLQH 2 tQHQL 2 tHHQX 2 tHLQZ 2 tW tDIS tV tHO tRO tFO tLZ tHZ tWC tCLH tCLL tRC tFC tDSU tDH Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock High Set-up Time before HOLD Active Clock High Set-up Time before HOLD not Active Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Low-Z HOLD Low to Output High-Z Write Time 0 100 100 100 250 10 40 50 140 90 120 120 250 150 0 50 50 50 100 5 Parameter Min.4 D.C. 200 200 200 200 200 200 200 1 1 20 30 70 40 60 60 100 60 Max.4 2 Min.5 D.C. 90 90 100 90 90 90 90 1 1 Max.5 5 Unit MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. tCH + tCL 1 / fC. 2. Value guaranteed by characterization, not 100% tested in production. 3. To be characterized. 4. Current product: identified by Process Identification letter S. 5. New product: identified by Process Identification letter V.
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M95256
Table 20. AC Characteristics (M95256-W, temperature range 3)
Test conditions specified in Table 10 and Table 8 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH 1 tCL 1 tCLCH 2 tCHCL 2 tDVCH tCHDX tHHCH tHLCH tCHHL tCHHH tSHQZ 2 tCLQV tCLQX tQLQH 2 tQHQL 2 tHHQX 2 tHLQZ 2 tW
Note: 1. 2. 3. 4.
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency
Parameter
Min. D.C. 90 90 100 90 90 90 90
Max. 5
Unit MHz ns ns ns ns ns ns ns
S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time
tCLH tCLL tRC tFC tDSU tDH
Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock High Set-up Time before HOLD Active Clock High Set-up Time before HOLD not Active
1 1 20 30 70 40 60 60 100 60 0 50 50 50 100 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Low-Z HOLD Low to Output High-Z Write Time
tCH + tCL 1 / fC. Value guaranteed by characterization, not 100% tested in production. To be characterized. New product: identified by Process Identification letter V.
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M95256
Table 21. AC Characteristics (M95256-S)
Test conditions specified in Table 10 and Table 9 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH 1 tCL 1 tCLCH 2 tCHCL 2 tDVCH tCHDX tHHCH tHLCH tCHHL tCHHH tSHQZ 2 tCLQV tCLQX tQLQH 2 tQHQL 2 tHHQX 2 tHLQZ 2 tW
Note: 1. 2. 3. 4. 5.
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency
Parameter
Min.4,5 D.C. 200 200 200 200 200 200 200
Max.4,5 2
Unit MHz ns ns ns ns ns ns ns
S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time
tCLH tCLL tRC tFC tDSU tDH
Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock High Set-up Time before HOLD Active Clock High Set-up Time before HOLD not Active
1 1 40 50 140 90 120 120 250 150 0 100 100 100 250 10
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Low-Z HOLD Low to Output High-Z Write Time
tCH + tCL 1 / fC. Value guaranteed by characterization, not 100% tested in production. To be characterized. This product is under development. For more infomation, please contact your nearest ST sales office. Preliminary data.
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M95256
Figure 16. Serial Input Timing
tSHSL S tCHSL C tDVCH tCHDX D MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
High Impedance
AI01447C
Figure 17. Hold Timing
S tHLCH tCHHL C tCHHH tHLQZ Q tHHQX tHHCH
D
HOLD
AI02032
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M95256
Figure 18. Output Timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D
ADDR.LSB IN
tCLQV tCLQX
tCL
tSHQZ
LSB OUT
AI01449D
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M95256
PACKAGE MECHANICAL PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
b2 A2 A1 b e A L
E
c eA eB
D
8
E1
1 PDIP-B
Notes: 1. Drawing is not to scale.
PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm Symb. Typ. A A1 A2 b b2 c D E E1 e eA eB L 3.30 2.92 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 7.62 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 - - 4.95 0.56 1.78 0.36 10.16 8.26 7.11 - - 10.92 3.81 0.130 0.115 0.130 0.018 0.060 0.010 0.365 0.310 0.250 0.100 0.300 Min. Max. 5.33 0.015 0.115 0.014 0.045 0.008 0.355 0.300 0.240 - - 0.195 0.022 0.070 0.014 0.400 0.325 0.280 - - 0.430 0.150 Typ. Min. Max. 0.210 inches
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M95256
SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Note: Drawing is not to scale.
SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm Symb. Typ. A A1 B C D E e H h L N CP 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
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M95256
SO8 wide - 8 lead Plastic Small Outline, 200 mils body width, Package Outline
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
Note: Drawing is not to scale.
SO8 wide - 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data
mm Symb. Typ. A A1 A2 B C D E e H L N CP 1.27 0.20 0.35 - 5.15 5.20 - 7.70 0.50 0 8 0.10 0.10 Min. Max. 2.03 0.25 1.78 0.45 - 5.35 5.40 - 8.10 0.80 10 0.050 0.008 0.014 - 0.203 0.205 - 0.303 0.020 0 8 0.004 0.004 Typ. Min. Max. 0.080 0.010 0.070 0.018 - 0.211 0.213 - 0.319 0.031 10 inches
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M95256
PART NUMBERING Table 22. Ordering Information Scheme
Example: Device Type M95 = SPI serial access EEPROM Device Function 256 = 256 Kbit (32768 x 8) Operating Voltage blank = VCC = 4.5 to 5.5V W = VCC = 2.5 to 5.5V S = VCC = 1.8 to 3.6V Package BN = PDIP8 (0.25 mm frame) MN1 = SO8 (150 mil width) MW = SO8 (200 mil width) Temperature Range 6 = -40 to 85 C 3 = -40 to 125 C Option T = Tape & Reel Packing
Note: 1. New product: identified by Process Identification letter V.
M95256
-
W MW 6
T
For a list of available options (speed, package, etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Office.
Table 23. How to Identify Current and New Products by the Process Identification Letter
Markings on Current Products1 95256W6 ANNYWWS Markings on New Products 95256W6 ANNYWWV
Note: 1. This example comes from the S08 package. Other packages have similar information. For further information, please ask your ST Sales Office for Process Change Notice PCN MPG/EE/0038 (PCEE0038).
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M95256
REVISION HISTORY Table 24. Document Revision History
Date 17-Nov-1999 07-Feb-2000 22-Feb-2000 15-Mar-2000 29-Jan-2001 Rev. 2.1 2.2 2.3 2.4 2.5 Description of Revision New -V voltage range added (including the tables for DC characteristics, AC characteristics, and ordering information). New -V voltage range extended to M95256 (including AC characteristics, and ordering information). tCLCH and tCHCL, for the M95xxx-V, changed from 1s to 100ns -V voltage range changed to 2.7-3.6V Lead Soldering Temperature in the Absolute Maximum Ratings table amended Illustrations and Package Mechanical data updated Correction to header of Table 12B TSSOP14 Illustrations and Package Mechanical data updated Document promoted from Preliminary Data to Full Data Sheet Announcement made of planned upgrade to 10 MHz clock for the 5V, -40 to 85C, range. M28128 split off to its own datasheet. Data added for new and forthcoming products, including availability of the SO8 narrow package. Omission of SO8 narrow package mechanical data remedied -V voltage range removed
12-Jun-2001 08-Feb-2002 09-Aug-2002 24-Feb-2003 26-Jun-2003
2.6 2.7 2.8 2.9 2.10
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M95256
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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